1. Field of the Invention PA1 2. Description of the Related Art
The invention relates to a semiconductor device, and more particularly to a semiconductor device including an electrically erasable programmable read only memory having a two-gate structure of a floating gate and a control gate deposited on the floating gate.
An electrically erasable programmable read only memory (hereinafter, referred to simply as "EEPROM") generally includes, as a memory cell, MISFET memory transistor having a two-gate structure of a floating gate and a control gate formed on the floating gate. Data is written into or eliminated from the two-gate type EEPROM by introducing electric charges into or discharging electric charges from a floating gate.
For instance, data is written into the two-gate type EEPROM by introducing channel hot electrons, generated in drain regions, into a floating gate, whereas data is eliminated from EEPROM by introducing electrons into a source, for instance, by virtue of Fowler-Nordheim tunneling.
A conventional method of fabricating a two-gate type memory cell array is explained hereinbelow with reference to FIGS. 1, 2 and 3A to 3D, wherein FIG. 1 is a plan view of a conventional two-gate type memory cell array, FIG. 2 is a plan view illustrating the memory cell array being fabricated, and FIGS. 3A to 3D are cross-sectional views of the memory cell array taken along the line III--III in FIG. 1, showing respective steps of a method of fabricating the memory cell array.
As illustrated in FIG. 3A, a p-type well 2 is formed in a p-type semiconductor substrate 1 in a region where a memory cell array is to be formed. Then, a plurality of field insulating films 3 is formed in the form of islands by selective oxidation. The field insulating films 3 are not illustrated in FIG. 3A, but are illustrated in FIG. 2.
Then, a first gate insulating film 4 is formed all over the p-type well 2, and a first polysilicon layer 5a is formed all over the first gate insulating film 4 for forming a floating gate. Then, impurities such as phosphorus (P) are doped into the first polysilicon layer 5a by thermal diffusion or ion-implantation to thereby lower a resistance of the first polysilicon layer 5a. Then, as illustrated in FIG. 2, the first polysilicon layer 5a is patterned into a plurality of layers 5a in parallel with each other so that the layers 5a extend perpendicularly to word lines which will be formed later, in order to define a width thereof in a direction of a channel width of a floating gate.
Then, a second gate insulating film 6 is formed all over the product, and a second polysilicon layer 7a is formed over the second gate insulating film 6. Then, as illustrated in FIG. 3A, a patterned photoresist film 18a is formed on the second polysilicon layer 7a by photolithography and dry etching. The photoresist film 18a has a pattern for forming word lines.
Then, as illustrated in FIG. 3B, the second and first polysilicon layers 7a and 5a are patterned with the patterned photoresist film 18a being used as a mask, to thereby form control gates 7 and floating gates 5. After removal of the photoresist film 18a, impurities such as arsenic (As) are ion-implanted into the product with the deposited gates 5 and 7 and the field insulating films 3 being used as a mask, to thereby form drain regions 8a and source regions 8b.
Then, as illustrated in FIG. 3C, sidewall spacers 9 are formed around a sidewall of the deposited gates 5 and 7 of each of memory cells in order to cause MOS transistors located outside memory cell array regions to have a LDD-structure. Thereafter, a first interlayer insulating film 10 is deposited all over the product. The first interlayer insulating film 10 is composed of boron phospho silicate glass (BPSG), and has a thickness in the range of 6000 to 8000 angstroms.
Then, there is formed a photoresist film 18e having a hole above the drain region 8a. Then, the first interlayer insulating film 10 is etched with the photoresist film 18e being used as a mask, to thereby form a contact hole 11 leading to the drain region 8a.
After removal of the photoresist film 18e, aluminum alloy is deposited by sputtering by a thickness in the range of 4000 to 6000 angstroms. Then, the aluminum alloy is patterned by photolithography and dry etching to thereby form bit lines 12 extending perpendicularly to the word lines. Then, the product is entirely covered with a passivation film 16 composed of PSG and having a thickness of about 5000 angstroms. Thus, there is completed a memory cell array.
While the above-mentioned method is being carried out, a region 3a (a hatched region in FIG. 2) which is sandwiched between the field insulating films 3 and will become a source region is exposed to etching twice, namely, when the first polysilicon layer 5a is patterned and when the second polysilicon layer 7a is patterned. When the first polysilicon layer 5a is patterned, the region 3a is covered merely with the thin first gate insulating film 4 after the first polysilicon layer 5a has been etched. Hence, the first gate insulating film 4 is first removed, and then, the p-type semiconductor substrate 1 is undesirably etched. In addition, when the second polysilicon layer 7a is patterned, the region 3a is covered merely with the thin second gate insulating film 6 after the second polysilicon layer 7a has been etched. Hence, the p-type semiconductor substrate 1 is undesirably further etched.
As a result, as illustrated in FIG. 4 which is a cross-sectional view taken long the line IV--IV in FIG. 1, there is formed an undesirable recess 19 at a surface of the semiconductor substrate 1. The undesirable recess 19 causes junction leakage therein, which a problem that data-writing and data-eliminating properties are deteriorated.
If a diffusion layer had a depth shallower than a depth of the recess 19, there is formed a breakage in a source region at the recess 19, since impurities are not ion-implanted into an inner sidewall of the recess 19. This causes a reduction in a fabrication yield.
The above-mentioned problem can be solved by a semiconductor device structure as suggested in Japanese Unexamined Patent Publications Nos. 3-52267 and 3-126266, for instance. Hereinafter is explained the suggested structure with reference to FIGS. 5, 6, 7 and 8A to 8D, wherein FIG. 5 is a plan view of the suggested memory cell array, FIG. 6 is a cross-sectional view taken along the line VI--VI in FIG. 5, FIG. 7 is a cross-sectional view taken along the line VII--VII in FIG. 5, and FIGS. 8A to 8D are cross-sectional views taken along the line VI--VI in FIG. 5, showing respective steps of a method of fabricating the suggested memory cell array.
The suggested memory cell array is characterized by that a plurality of the field insulating films 3 extend perpendicularly to the word lines 7, and that the common source line 17a connecting the source regions 8b to each other in a direction in which the word lines 7 extend is formed to extend perpendicularly to the field insulating films 3. Hereinafter is explained a method of fabricating the suggested memory cell array, with reference to FIGS. 8A to 8D.
As illustrated in FIG. 8A, a p-type well 2 is formed in a p-type semiconductor substrate 1 by introducing p-type impurities into the semiconductor substrate 1 and thermally diffusing the p-type impurities in the semiconductor substrate 1. Then, a plurality of field insulating films 3 are formed on a principal surface of the p-type well 2 by selective oxidation so that the field insulating films 3 extend in parallel with one another, but perpendicularly to word lines which will be formed later. The field insulating films 3 are not illustrated in FIG. 8A, but only illustrated in FIG. 5.
Then, a first gate insulating film 4 and then a first polysilicon layer 5a are formed all over the product. Then, impurities such as phosphorus (P) are ion-implanted into the first polysilicon layer 5a to thereby lower a resistance of the first polysilicon layer 5a. Then, as illustrated in FIG. 2, the first polysilicon layer 5a is patterned into a plurality of layers 5a in parallel with each other in order to define a width thereof in a direction of a channel width of a floating gate. When the first polysilicon layer 5a is patterned, the thick field insulating films 3 exist below a region where the first polysilicon layer 5a is etched, which ensures that the substrate 1 is not etched, and hence a recess such as the recess 19 illustrated in FIG. 4 is not formed.
Then, a second gate insulating film 6 is formed all over the product, and a second polysilicon layer 7a is formed over the second gate insulating film 6. Then, impurities such as phosphorus (P) are ion-implanted into the second polysilicon layer 7a to thereby lower a resistance thereof Then, as illustrated in FIG. 8A, a patterned photoresist film 18a is formed on the second polysilicon layer 7a by photolithography and dry etching. The photoresist film 18a has a pattern for forming word lines.
Then, as illustrated in FIG. 8B, the second and first polysilicon layers 7a and 5a are patterned by etching with the patterned photoresist film 18a being used as a mask, to thereby form control gates 7 and floating gates 5. After removal of the photoresist film 18a , n-type impurities are ion-implanted into the product with the deposited gates 5 and 7 and the field insulating films 3 being used as a mask, to thereby form drain regions 8a and source regions 8b.
Then, as illustrated in FIG. 8C, sidewall spacers 9 are formed around a sidewall of the deposited gates 5 and 7 of each of memory cells. Thereafter, a first interlayer insulating film 10 is deposited all over the product by chemical vapor deposition (CVD). The first interlayer insulating film 10 is composed of silicon dioxide. Then, the first interlayer insulating film 10 is etched in selected regions to thereby form contact holes C1 reaching a surface of the source regions 8b and contact holes C2 reaching a surface of the drain regions 8a.
Then, as illustrated in FIG. 8D, an electrically conductive layer composed of polysilicon is formed all over the product, and then patterned to thereby form a common source line 17a and an extended bit line 17b. The common source line 17a connects the source regions 8b in a direction in which the word lines extend. The extended bit line 17b makes electrical contact with the drain region 8a through the contact hole C2, and covers a portion of the first interlayer insulating film 10 around the contact hole C2 therewith. The electrically conductive layer from which the common source line 17a and the extended bit line 17b are formed may be composed of refractory metal, silicide thereof, or polycide thereof, as well as polysilicon.
Then, a second interlayer insulating film 13 composed of BPSG is deposited all over the product. Thereafter, a photoresist film 18c is formed, and then, patterned by photolithography and dry etching so as to have an opening above the extended bit line 17b. Then, the second interlayer insulating film 13 is etched with the patterned photoresist film 18c being used as a mask, to thereby form through-holes 14 reaching the extended bit line 17b.
After removal of the photoresist film 18c, aluminum alloy is deposited by sputtering. Then, the aluminum alloy is patterned by photolithography and dry etching to thereby form bit lines 12 (see FIGS. 5, 6 and 7) extending perpendicularly to the word lines. Then, the product is entirely covered with a passivation film 16 (see FIGS. 4, 6 and 7) composed of PSG. Thus, there is completed a non-volatile semiconductor memory device as illustrated in FIGS. 4 to 7.
In accordance with the above-mentioned method, when the first polysilicon layer 5a is etched, the thick field insulating films 3 exist below a region to be etched. When the second and first polysilicon layers 7a and 5a are patterned to thereby form the control gate 7 and the floating gate 5, a region where only a single polysilicon layer is etched is a region located above the field insulating regions 3. Hence, the above-mentioned undesirable recess 19 caused by etching a polysilicon layer is not formed. Accordingly, there is solved a problem that junction leakage junction leakage occurs due to the recess, and resultingly data-writing and data-eliminating properties are deteriorated, and that a fabrication yield due to the breakage in a source region is reduced.
A semiconductor device including a high-rate CMOS logic circuit is generally designed to have two or more wiring layers. When a non-volatile memory is formed on a common semiconductor substrate on which a high-rate CMOS logic circuit is also formed, it is required that an increase in the number of additional fabrication steps is avoided and that the non-volatile memory is small in size, in order to reduce fabrication costs and integrate the device in a higher density.
In the conventional method having been explained with reference to FIGS. 5, 6, 7 and 8A to 8D, the common source line is formed of the electrically conductive layer composed of electrically conductive material such as polysilicon, after the contact hole has been formed. Hence, the above-mentioned conventional method has a problem that the number of additional fabrication steps is increased relative to the number of steps for fabricating CMOS logic circuit having two or more wiring layers, and hence, fabrication costs are also increased.
In addition, since the common source line is formed of an electrically conductive layer composed of polysilicon, the common source line unavoidably has high resistivity, which causes problems that data-writing and data-eliminating properties of a non-volatile memory are deteriorated, and that a speed at which a memory cell reads out data is reduced.
The common source line may be designed to have a smaller resistance by increasing an area of the electrically conductive layer and/or forming a backing wiring layer composed of aluminum. However, this makes it difficult to reduce a size of a memory cell, and reduce fabrication costs per a chip.